The low-power challenge
In our connected and mobile world, IC designers are striving to save µA or even nA of power consumption to extend battery usage without recharge. IoT applications bring the need for LP to new heights involving the adoption of more complex SoC architectures based on multiple power domains, which also require embedding the whole power regulation network and optimizing carefully the always-on domain.
Such advanced SoC architectures significantly increase design complexity and may thus severely impact Time-to-Market and costs. As the power domains are dynamically switched on and off, the selection of the SoC architecture must be performed in full awareness of noise issues.
The successful mix to get a low-power "dish"
SoC designers may now take advantage of a complete and consistent offering for designing safely and fast an ultra-low power SoC. The effectiveness of this complete and consistent offering is proven with the "Taishan demochip" designed in partnership with TSMC at 55 nm uLP eF. Such a unique combination partakes in ensuring:
- the best Time-To-Market (TTM) with the lowest risks,
- the optimization of SoC performances with the best trade-off between silicon area, BoM cost, mode transition leadtime and power consumption.
Low-power Silicon IPs to deal with low-power requirement in sleep and in active modes
SoC Fabric IPs to securely speed-up the implementation of the power regulation and of the mode control network of any low-power SoC
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(Always-On power domain)
EDA platform to explore SoC architectures which satisfy the performance requirements – area, BoM, power consumption in sleep and in active mode… - while taking into consideration noise on power supplies generated during mode transitions and in steady state
EDA platform to perform all along the design flow the Noise Propagation Checks and the Mode Transition Checks both providing IP Compatibility Insurance with respect to a power supply
Structured design methodologies for dealing with the LP optimization of an SoC architecture and for mastering the implementation of a LP SoC in order to streamline and speed-up the design steps up to the tape-out while preventing excessive or insufficient design margins, which may be detrimental to silicon area and BoM cost.
Streamlining the safe construct of a low-power SoC design with multiple power domains involves putting in place a proper design flow. Our Architectural Guidelines, Integration Guidelines and Rules provided together with a low power SoC User Guide, complement the reference flow (low-power and PPA) of TSMC and the application notes of EDA providers. The effectiveness of this know-how, which has been demonstrated with Taishan Demochip, partakes in accelerating and in securing the Time-to-Market of ultra-low power SoCs designed with multiple power domains.
Definition of SoC functional blocks
Identification of operating frequencies
Definition of the Power Management Network
Identification of the control network and definition of mode change sequences
Identification of Application schematics
Good Dish: Taishan
Why a demochip?
A testchip and a demochip do not have the same objectives
A testchip permits to qualify one or several individual Virtual Components (ViC) in order to prove the conformity between their specification and the measurement results on silicon. It thus serves to provide a full characterization report to raise the confidence of users of Silicon IP components.
A demochip goes beyond a testchip. Indeed, it permits to prove the dynamic interplay between several Virtual Components. A demochip serves to give confidence in the overall construct of a SoC architecture proven by dynamical tests involving multiple components.
Demochip proven Taishan
The TaiShan demochip is proving the construct of a SoC partitioned in multiple power domains for achieving a very low power consumption in both sleep and active modes by demonstrating:
- the safe interplay of the ultra-low power silicon IPs embedded in the Demochip
- the robustness of Fabrics IPs for constructing the Power Regulation Network, incl. its mode control
- the accuracy of simulations for dealing with Mode Transition Checks
- the efficiency of Architectural Guidelines and of Integration Guidelines and Rules to speed-up Time-To-Market
To achieve this goal, Taishan demochip specification is representative of an ultra-low power applications such as Internet of Things (IoT), Wearable, MCUs..., and thus embed the power regulation networks together with the control of power modes (incl. the start-up mode).
As shown in the synopsis below, Taishan demochip combines a set of Feature IPs (Voice Activity Detector , sDAC, 32-bit RISC Microcontroller and Cache Controller), Foundation IPs (Standard cells library & Memories) and Fabric IPs (Power Gating solution, Voltage regulators and Mode Activity Controller).
It relies on the TSMC 55 nm uLP eFlash to take advantage of the low-voltage capabilities to achieve the minimal power consumption in active mode down to 0.9 V (+/-10%) and in sleep mode with a retention voltage down to 0.55 V.
The safe interplay between all these virtual components (ViCs) is proven with activitity scenarios which are handled by the Mode Activity Controller built with MAESTRO.
Furthermore, Taishan demochip enables to ascertain the relevance and the accuracy of simulations performed with PowerVision™ to assess the impact of noise generated during mode transitions and propagated on the power supply. The noise generated during the mode transition (on-off-ret) on the power regulation network indeed implies to perform Mode Transition Checks at the earliest design stage and all along the design flow to both prevent performance drops or even functionality issues and to avoid excessive design margins.
If you want more information about Taishan Demochip: CLICK HERE