SMASH Mixed-Signal Simulator

SMASH is a seamless IC-PCB mixed-signal simulator enabling the development and verification of analog and mixed-signal Silicon IPs and Integrated Circuits (IC) as well as the optimization of application schematics thanks to its unique multi-domain capabilities.

With the mixed-signal simulator SMASH, designers benefit from innovative features which enable efficient and fast detection of design defects with a fine control for tuning the speed accuracy trade-offs.

These features address the request from designers to rely on a simulator which can truly help them improve their design productivity for as faster and safer time-to-fab. Indeed, the analysis of the time spent by engineers to complete their designs shows that most of their valuable time can be saved with a simulator offering appropriate design bug detection features as well as debugging features.

SMASH is the mixed-signal simulator of choice for designers eager to improve their productivity!

If your challenge is to reduce your application’s power consumption and to reduce its cost, you need PowerVision™, a game-changer for mixed-signal circuit integration & verification. Learn more...

Key Strengths of the Mixed-Signal Simulator SMASH

  • State-of-the-art single kernel for easy mixing of multi-language, mixed-signal and multi-domain descriptions
    • Support of the most common modeling languages: SPICE, (System)Verilog, VHDL, Verilog-A(MS), VHDL-AMS...
    • Support of different SPICE flavors including HSPICE compatibility
    • Automatic insertion of configurable interface devices as needed between logic and analog parts
  • Dynamic link with the schematic editor SLED
    • Back-annotation of operating-point states to the schematic
    • Cross-probing to quickly localize a signal curve
  • Simultaneous display of analog and logic simulation results in an interactive waveform viewer both interactively during the analysis runtime and in post-processing
  • Easy setup of trade-off between speed and accuracy plus added-value features for design bug detection and eradication
  • IEEE model encryption for source code protection in order to exchange data safely
  • Simulation results calibrated against Silicon measurements
  • Required flexibility to model the IC with its application schematics to optimize system performance as early as possible in the design cycle and before any fabrication
  • Interoperability
    • Compatibility with frameworks and complementary solutions (HSPICE, ModelSim, PSpice) to add new modeling and simulation capabilities to an existing design flow
    • SMASH integrated as Laysim in Laytools suite from TexEDA
    • Schematic-driven Layout between SLED and DW2000 from Design Workshop Technologies
    • Easy communication between S-Edit from Tanner EDA and SMASH
SMASH languages
  • Receive our catalog

  • Associated offering